1. Field
Example embodiments relate to a method of operating a semiconductor memory device, a semiconductor memory device, and/or a portable media system including the same.
2. Description of Related Art
Internal circuits of a conventional semiconductor memory device are initialized to voltage levels set through initialization in response to an external power voltage EVC applied from an external source. An initialization signal generated from an initializing circuit controls initialization of an internal circuit. The initialization signal generally determines a logic level of a latch circuit incorporated in the internal circuit.
Initialization signals include a first initialization signal and a second initialization signal. As a voltage level of the external power voltage EVC is increased during a power-up operation, a voltage level of the first initialization signal is increased to a desired, or alternatively, a predetermined level. After the first initialization signal reaches the desired, or alternatively, the predetermined level, the voltage level of the first initialization signal is fixed at a low level. As a voltage level of an internal power voltage IVC is increased, a voltage level of the second initialization signal is increased to a desired, or alternatively, a predetermined level. After the second initialization signal reaches the desired, or alternatively, the predetermined level, the voltage level of the second initialization signal is fixed at a low level.
If retaining data in a standby mode is not necessary, a semiconductor memory device, e.g., a dynamic random access memory (DRAM), enters a deep-power-down mode (hereinafter referred to as “DPD mode”) in which power consumption is reduced or minimized by interrupting the operation of a circuit for performing self-refresh cycles, or by not operating an internal voltage generator in the memory device.
FIG. 1 is a schematic timing diagram illustrating an operation of a conventional semiconductor memory device.
Referring to FIG. 1, the semiconductor memory device performs a power-up operation for a period of time 0-t1, the semiconductor memory device operates normally for a period of time t1-t2, the semiconductor memory device operates in a DPD mode for a period of time t2-t3, and the semiconductor memory device operates normally again after t3. During the DPD mode, a deep-power-down control signal PDPDE is enabled to a logic high level.
A first initialization signal VCCHB_IVC based on an internal power voltage IVC is generated if the semiconductor memory device performs a power-up operation, if the semiconductor memory device enters the DPD mode, and if the semiconductor memory device exits from the DPD mode.
The first initialization signal VCCHB_IVC (see a portion indicated by reference character “a” in FIG. 1), generated if the semiconductor memory device enters the DPD mode at time t2, may undesirably generate leakage current in the internal circuit.